1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that drives an external load, more particularly to a semiconductor integrated circuit with improved electromagnetic compatibility.
2. Description of the Related Art
Electromagnetic compatibility (EMC) is an important issue for integrated circuits in general and is becoming a critical issue for the integrated circuits used in display devices such as liquid crystal displays (LCDs). The signal lines connecting the driving circuits of an LCD to the liquid crystal cells in its liquid crystal panel readily pick up electromagnetic interference (EMI) generated by nearby electrical and electronic devices. As the level of integration of the driver circuits increases and the number of output signal lines per driver increases, reducing susceptibility to such interference becomes essential. There are especially stringent EMC testing requirements for the LCDs used in mobile telephones, in which the effect of wireless signals transmitted by the telephone must be considered.
Among the many other uses to which LCDs are put, LCDs with comparatively large liquid crystal panels are now used in automobiles. The electrically noisy automobile environment places further EMC requirements on LCD driver circuits.
FIG. 1 shows a liquid crystal panel 50 and part of a conventional LCD driver 59. The liquid crystal panel 50 is, for example, a super-twisted nematic panel with a matrix of wiring including segment (SEG) signal lines 51 and common (COM) signal lines 52 that cross at liquid crystal cells 53. Only one segment signal line 51, common signal line 52, and liquid crystal cell 53 are shown. The segment signal line 51 and common signal line 52 are connected to the driver 59 by respective interconnecting lines 54, 55. Application of certain voltages to the segment signal line 51 and common signal line 52 controls the liquid crystal cell 53 to display a pixel in an image.
The driver 59 includes a segment driver 60 and a common driver 70 with respective output stages 63, 73 and electrostatic discharge (ESD) protection circuits 64, 74. The output stages 63, 73 select voltages generated by a voltage dividing circuit 62 and output the selected voltages to respective output terminals 66, 76, to which the interconnecting lines 54, 55 are connected.
The voltage dividing circuit 62 includes a p-channel metal-oxide-semiconductor (PMOS) transistor 62a, three resistors 62b, 62c, 62d, and an n-channel metal-oxide-semiconductor (NMOS) transistor 62e connected in series between a power supply terminal to which a positive supply voltage VDD is applied and ground terminal to which a ground voltage VSS is applied. When the transistors 62a, 62e are turned on, the resistors 62b, 62c, 62d function as a voltage divider and the voltage dividing circuit 62 outputs four voltages V1, V2, V3, V4, of which V1 is equal to VSS and V4 is equal to VDD.
The output stage 63 of the segment driver 60 includes a pair of analog switches 63a, 63b, each having a PMOS transistor and an NMOS transistor connected in parallel. When switched on by control signals (not shown), these analog switches 63a, 63b pass voltages V3 and V2, respectively, to the segment output terminal 66. The output stage 63 also includes a PMOS transistor 63c and an NMOS transistor 63d that can be switched on pass voltages V4 and V1, respectively, to the segment output terminal 66.
The ESD protection circuit 64 includes a pair of diodes 64a, 64b connected to the internal signal line leading from the output stage 63 to the segment output terminal 66 to limit the voltage on this internal signal line to the range between VDD and VSS.
The output stage 73 and ESD protection circuit 74 of the common driver 70 have a similar configuration, including analog switches 73a, 73b, a PMOS transistor 73c, an NMOS transistor 73d, and a pair of diodes 74a, 74b. 
When, for example, the segment driver 60 is controlled to output voltage V3 from output terminal 66 and the common driver 70 is controlled to output voltage V2 from output terminal 76, a voltage equal to the difference (V3−V2) is applied across liquid crystal cell 53, causing a pixel to be displayed at a corresponding intensity level.
Besides functioning as signal lines for the voltages output by the driver 59, the segment signal line 51 and interconnecting line 54 form a single continuous antenna-like conductor that can easily pick up stray electromagnetic interference, indicated by the arrow marked EMI in FIG. 1. Similarly, the common signal line 52 and interconnecting line 55 form another antenna-like conductor that can pick up electromagnetic interference. Such interference effects can take the voltages on the interconnecting lines 54, 55 outside the range between VSS and VDD. The ESD protection circuits 64, 74 protect the driver 59 from damage that could be caused by voltages higher than VDD or lower than VSS.
As a further countermeasure to EMI, in Japanese Patent Application Publication No. 2003-257971 Matsumoto discloses a semiconductor device with dummy wiring interspersed among its internal signal lines. The dummy wiring is held at a fixed reference potential and provides a shielding effect.
A problem with the conventional LCD in FIG. 1 is that when electromagnetic interference is present, the ESD protection circuits 64, 74 can alter the voltages output by the driver 59 and thereby alter the intensity levels of displayed pixels.
Suppose, for example, that while segment driver 60 is driving output terminal 66 at voltage V3, the segment signal line 51 and interconnecting line 54 pick up electromagnetic noise, causing the voltage on segment signal line 51 and interconnecting line 54 to oscillate with the interference waveform IW1 in FIG. 2. Although the oscillations take this waveform above V4 (VDD), the average voltage on segment signal line 51 and interconnecting line 54 is still V3. The VDD clamping effect of ESD protection circuit 64, however, trims the excursions above V4 to produce the modified interference waveform IWX, thereby decreasing the average voltage output from terminal 66 by an amount ΔV3.
If common driver 70 is simultaneously driving output terminal 76 at voltage V2, the same interference waveform, superimposed on the voltage V2 on common signal line 52 and interconnecting line 55, stays below V4 but also goes below V1 (VSS), as shown in FIG. 3. The VSS clamping effect of ESD protection circuit 74 raises the average voltage output from output terminal 76 by an amount ΔV2.
The average voltage applied across liquid crystal cell 53 is accordingly not the intended voltage (V3−V2) but a voltage reduced from this value by the sum of ΔV2 and ΔV3, resulting in a pixel with an unintended intensity level. Electromagnetic interference thus visibly disturbs the displayed image.
Since the dummy wiring proposed by Matsumoto fails to shield the segment signal line 51, common signal line 52, and interconnecting lines 54, 55, it fails to reduce this visible image disturbance.